Processor hardware performing SIMD/vector calculations.

Processor capable of executing multiple instructions per cycle.

Cache whose contents are duplicated in another cache level.

Hardware converting machine instructions into internal operations.

Hardware executing one instruction across multiple data elements.

Sequential hardware stages used to process instructions.

Cache architecture minimizing duplicated data between levels.

Hardware retrieving instructions for processor execution.

SIMD integer-processing hardware associated with x86 processors.

Individual step within a processor pipeline.