Simultaneous multithreading technology allowing multiple logical threads per core.

Intel's implementation of simultaneous multithreading.

Physical package containing one or more processor dies.

Processor cache generally larger and slower than L1.

Hardware predicting the outcome of processor branches.

Processor hardware storing data to memory.

Processor stage permanently committing completed instructions.

Larger processor cache often shared by multiple cores.

Cache storing predicted branch destination information.

Processor hardware handling branch operations.