Processor hardware storing data to memory.

Processor stage permanently committing completed instructions.

Larger processor cache often shared by multiple cores.

Cache storing predicted branch destination information.

Processor hardware handling branch operations.

Processor hardware executing instructions in an optimized order.

Additional cache level present in some architectures.

Hardware predicting return addresses for function calls.

Processor hardware performing SIMD/vector calculations.

Processor capable of executing multiple instructions per cycle.