Hardware register separating pipeline stages.

Cache writing modified data to lower memory only when necessary.

Hardware tracking out-of-order instructions until retirement.

Hardware supporting Advanced Vector Extensions.

Cache immediately forwarding writes to lower-level memory.

Hardware holding instructions waiting for execution resources.

Hardware supporting AVX2 vector instructions.

Number of locations where a cache block may be stored.

Hardware storage containing processor registers.

Hardware supporting 512-bit AVX vector operations.