Hardware predicting the outcome of processor branches.
Hardware predicting the outcome of processor branches.
Processor hardware predicting and fetching future memory accesses.
Loading predicted data into a cache before it is requested.
Access where requested data is found in the cache.
Access where requested data is absent from the cache.
Cache allowing a block to occupy any cache location.
Cache allowing blocks multiple locations within a set.
Cache allowing each block only one possible location.
Number of locations where a cache block may be stored.
Cache immediately forwarding writes to lower-level memory.
Everything is a system, and every system contains systerms.