hardware system

Pipeline conflict caused by data dependencies.

Temporary halt caused by an unresolved dependency or resource conflict.

Discarding incorrectly speculated pipeline instructions.

Hardware register separating pipeline stages.

Individual step within a processor pipeline.

Sequential hardware stages used to process instructions.

Processor capable of executing multiple instructions per cycle.

Processor hardware executing instructions in an optimized order.

Processor stage permanently committing completed instructions.

Physical random-number generation circuitry.