Smallest common programmable unit in NAND flash.

Technique distributing accesses across multiple memory banks.

Fourth-generation DDR memory technology.

Enhanced HBM3 memory technology.

Group of NAND pages erased together.

Process that restores charge in DRAM cells.

Fifth-generation DDR memory technology.

Fast memory commonly used for CPU caches.

Internal NAND region containing multiple blocks.

Signal historically used to select a DRAM row.