hardware system

Hardware managing NAND flash operations.

Physical package containing one or more flash dies.

Individual silicon chip containing flash memory arrays.

Internal NAND region containing multiple blocks.

Group of NAND pages erased together.

Smallest common programmable unit in NAND flash.

NAND concept storing five bits per cell.

NAND storing four bits per memory cell.

NAND storing three bits per memory cell.

NAND storing multiple bits, commonly two, per cell.