Rambus dynamic random-access memory.

Extended-data-out dynamic memory.

Fast-page-mode memory.

Nonvolatile random-access memory.

Magnetoresistive random-access memory.

Ferroelectric random-access memory.

Resistive random-access memory.

Phase-change memory.

Flash memory using NOR architecture.

Flash memory using NAND architecture.

NAND flash storing one bit per cell.

NAND flash storing multiple bits, commonly two, per cell.

NAND flash storing three bits per cell.

NAND flash storing four bits per cell.

Proposed flash technology storing five bits per cell.

NAND flash with vertically stacked memory cells.

Vertically stacked NAND flash architecture.

Hardware managing flash-memory operations.

Controller managing NAND flash memory.

Hardware generating or checking error-correction codes.

Hardware implementing low-density parity-check correction.

Hardware distributing flash writes across memory cells.

Hardware or firmware subsystem reclaiming flash storage blocks.

System managing defective flash-memory blocks.

Layer mapping logical addresses to physical flash locations.

Stack of NAND memory dies in a package.

Chip managing system-memory communication.

Memory controller integrated into a processor.

Hardware buffering memory signals.

Register buffering memory command or address signals.

Circuit driving memory signals.

Physical-layer circuitry connecting a controller to memory.

Hardware calibrating high-speed memory interfaces.

Hardware providing signal termination for memory buses.

Timing signal used by memory.

Electrical paths carrying memory data.

Electrical paths carrying memory addresses.