Logical grouping of memory cells.

Memory using registers between memory controller and chips.

Static random-access memory that does not require refresh cycles.

Enhanced HBM2 memory technology.

Smallest unit storing a memory bit or state.

RAM using buffering to reduce electrical loading.

Synchronous dynamic random-access memory.

Third-generation High Bandwidth Memory.

Smallest binary data unit, representing 0 or 1.

RAM without an intermediate register or buffer.