hardware system

Memory module designed to reduce electrical loading.

RAM without an intermediate register or buffer.

RAM using buffering to reduce electrical loading.

Memory using registers between memory controller and chips.

Memory system using parity information for error detection.

Memory capable of detecting and correcting certain errors.

Rate at which memory can transfer data.

Set of delays controlling RAM operation.

Delay between a column request and returned memory data.

Delay before memory begins responding to a request.