PCI Express slot with four lanes.

PCI Express slot with eight lanes.

PCI Express slot with up to sixteen lanes.

Conceptual PCI Express configuration supporting thirty-two lanes.

Independent transmit/receive path in PCI Express.

PCIe component connecting the processor or chipset to devices.

Hardware connecting multiple PCIe devices or endpoints.

Device connecting different PCIe or bus domains.

PCI Express device at the end of a connection.

Hardware restoring PCIe signal quality over longer paths.

Device strengthening or conditioning PCIe signals.

Splitting one PCIe slot into multiple lane groups.

Capability to add or remove PCIe devices while operating.

First-generation PCI Express.

Second-generation PCI Express.

Third-generation PCI Express.

Fourth-generation PCI Express.

Fifth-generation PCI Express.

Sixth-generation PCI Express.

Seventh-generation PCI Express standard generation.

Established communication connection between PCIe components.

Process determining compatible link capabilities.

Signal-processing process compensating for channel loss.

Actual data carried by a PCIe transaction.

Formatted unit of data transmitted over PCIe.

Transaction Layer Packet used by PCI Express.

Data Link Layer Packet used for PCIe link management.

Mechanism preventing receiver buffer overflow.

Circuit increasing radio-frequency transmission power.

Antenna formed directly on a circuit board.

Flat directional antenna commonly used at high frequencies.

Hardware organizing and terminating network cables.

Power-management communication protocol based on SMBus.

Pulse-width modulation used for control and power applications.

Phase-locked loop used for clock generation and synchronization.

Programmable read-only memory that is normally programmed once.

Sensor detecting nearby objects or users.